Formal and Simulation Verification: Comparing and Contrasting the two Verification Approaches
M Girish, G Gopakumar, D S Divya · 2021
Simulation verification is the traditional verification method used in verifying the functionality of RTL designs. In this paper, we compare and contrast the simulation approach with the model checking assertion based formal verification methods. The tools used are Jaspergold and QuestaSim. The design used is an encoder block implementing the manchester encoding for the MIL 1553-b protocol which is widely used in applications