An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson · 2021
We describe a framework for automated generation of hybrid processor/accelerator systems comprising a RISC-V processor, and a coarse-grained reconfigurable array (CGRA) for realizing compute-kernel acceleration. CGRAs are programmable hardware platforms having an array of coarse ALU-like processing elements, and word-wide programmable interconnect. The proposed framework integrates CGRAs generated by the open-source CGRA-ME tool [1], with the RISC-V processor from the PULP project [2]. In an experimental study, we use the framework to generate RISC-V+CGRA systems that provide an order-of-magnitude speedup vs. software and considerable speedup vs. a vector processor on several applications by leveraging the CGRA spatial and pipeline parallelism. As CGRA-ME permits a variety of different CGRAs to be modelled and mapped to, we believe the proposed framework represents a powerful open-source platform, enabling a variety of new research on processor/CGRA system architectures and programming models.