Triple-Level-Cell/Single-Level-Cell Mix-Mode Operation Induced Data Retention Degradation in 3-D NAND Flash Memories
Yuheng Liu, Yu-Siang Yang, Chih-Yuan Tseng, Wei Li Lin, An-Chang Liu, Yu‐Cheng Hsu · IEEE Electron Device Letters · 2021
Compared to single-level-cell (SLC) mode operation, triple-level-cell (TLC) mode operation reduce NAND Flash lifetime due to its stronger program$/$erase ($\text{P}/\text{E}$) cycled-induced oxide degradation and narrower read margin between neighboring states. However, by measuring the evolution characteristics of raw bit error rate (RBER) and threshold voltage ($\text{V}_{\text {t}}$) shift during retention bake, TLC-erase$/$SLC-program mix-mode$\text{P}/\text{E}$sequences in 3-D NAND Flash memory exhibits significant retention deterioration compared with pure TLC-mode$\text{P}/\text{E}$schemes. Based on our measurement results, mix-mode operation may create more residual holes in the inter-gate spacing (IGS) region, giving rise to enhanced lateral migration of trapped charge in silicon nitride (SiN) storage layer and the larger$\text{V}_{\text {t}}$retention loss accordingly.