Improved BIST Design for Detecting Ageing Faults in Automotive ICs
Jyothishya Pallavi, Navya Mohan · 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC) · 2021
In VLSI, testing is a significant step to determine the presence of faults in a given chip/circuit. The number of safety-critical devices in automotive industries is increasing rapidly. To get functionally safe ICs for automotive applications, one needs to have a high quality and long-term reliability. Thus, the testing circuits ought to have highlights such as high fault coverage, in-field testing capacity and capacity to check long term reliability. This paper presents a scan based at-speed test with linear feedback shift register (LFSR) pattern generation and reordering algorithm. The pattern generation scheme used in BIST is driven by seed flipping LFSR for transition fault test coverage then power is reduced by using reordering scheme. The test applied to various ISCAS-85, 89 and ITC-99 circuits. The simulation results show an improved fault coverage and reduction in test power.