Novel architecture for floating point accumulator with cancelation error detection
E. Jamro, Agnieszka Dąbrowska-Boruch, Pawel Grzegorz Russek, Maciej Wielgosz, K. Wiatr · Bulletin of the Polish Academy of Sciences Technical Sciences · 2018
A floating point accumulator cannot be obtained straightforwardly due to its pipeline architecture and feedback loop.Therefore, an essential part of the proposed floating point accumulator is a critical accumulation loop which is limited to an integer adder and 16-bit shifter only.The proposed accumulator detects a catastrophic cancellation which occurs e.g. when two similar numbers are subtracted.Additionally, modules with reduced hardware resources for rough error evaluation are proposed.The proposed architecture does not comply with the IEEE-754 floating point standard but it guarantees that a correct result, with an arbitrarily defined number of significant bits, is obtained.The proposed calculation philosophy focuses on the desired result error rather than on calculation precision as such.