Northwest Laboratory for Integrated Systems, University of Washington, Semiannual Technical Report Number 1, July 1-November 8, 1991
Gaetano Borriello, Carl W. Ebeling, Lawrence Snyder · 1991
Contents: (1) Retiming of Level-Clocked Circuits; (2) Triptych - A new Field-Programmable Gate Array Architecture; (3) Subgraph Isomorphism; (4) Symbolic Timing Verification and High Level Synthesis; (5) Synthesis of Microcontroller-Based Embedded Systems; (6) Chaos Router; and (7) The MacTester.