Analyse formelle des programmes Ladder
Cláudio Belo Lourenço, Denis Cousineau, Florian Faissole, Claude Marché, David Mentré, Hiroaki Inoue · HAL (Le Centre pour la Communication Scientifique Directe) · 2021
Programmable logic controllers (PLC) are industrial digital computers used as automation controllers of manufacturing processes, such as assembly lines or robotic devices. The Ladder language, also known as Ladder Logic, is a programming language used to develop PLC software. Because of their widespread usage in industry, verifying that Ladder programs conform to their expected behaviour is of critical importance. In this work, we consider the description of the expected behaviour under the form of a timing chart, describing scenarios of execution. Our approach consists in translating the Ladder code and the timing chart into a program for the Why3 environment dedicated to deductive program verification. The verification proceeds by generating formal verification conditions, which are mathematical statements to be proved valid using automated theorem provers. The ultimate goal is two-fold: first, by obtaining a complete proof, we can verify the conformance of the Ladder code with respect to the timing chart with a high degree of confidence. Second, when the proof is not fully completed, we obtain a counterexample, illustrating a possible execution scenario of the Ladder code which does not conform to the timing chart.