Development of Low-Power and High-Speed On-Chip Clock Distribution System
正寛 一橋 · Kyushu University Institutional Repository (QIR) (Kyushu University) · 2020
Digital products such as smartphone, tablet, laptop, camera etc. are vital to modern societies.The integrated devices such as microprocessor, memory, transceiver and image sensor etc., operate based on some fundamental clocks.Hence, it is not too much to say that the fundamental clocks determine the overall performance of these digital devices.On-chip clock distribution systems play vital roles since it distributes the fundamental clocks to the whole chip.For instance, a global tree structure distributes the system clock to the whole chip and a differential signaling structure which is main scope of this dissertation distributes the I/O clock for high-speed serial links.However, these are the most power hungry block as well.A large portion of total power from 25% to 70% are dissipated by on-chip clock distributions in the case of microprocessors.With the increase of operating speed and length in recent digital systems, low-power and high-speed operation is becoming further challenging task due to the increase of jitter and power caused by multiple repeater stages.The goal of this dissertation is to propose the innovative solutions to overcome the above mentioned problems of on-chip clock distribution for high-speed serial links.The proposed bufferless LC resonant clock architecture directly drives on-chip clock distribution line without any buffers and repeaters.Thanks to the bufferless structure, the performance of the clock distribution is determined by the LC oscillator only.The proposed architecture is composed of three key features; Inductor, LC oscillator and on-chip transmission line design.The proposed inductor maximizes the performance of LC oscillator.The proposed LC oscillator mitigates the tradeoff of high-frequency, low-power operation and allows bufferless architecture.The proposed fully calculation-based on-chip transmission line modeling and optimization are able to find the optimized parameters such as metal width, space etc. instantaneously without any SPICE and EM (Electro-Magnetic) simulations.The proposed bufferless architecture which is directly connected to a 10-mm on-chip clock distribution line is fabricated in TSMC 0.18-μm 1-poly 6-metal CMOS process.The experimental results achieved 2.8-GHz oscillation frequency, 3.3-mA current consumption, -112.8 dBc/Hz phase noise which is comparable to the other state-of-theart LC oscillators in spite of the absence of buffers and repeaters.