A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools
Ming Ling, Hongxi Li, Xiang Yu · IEEE Embedded Systems Letters · 2021
A literal pool is normally used by a RISC processor to store constant values adjacent to the function that accesses them. Therefore, during a cache line filling, the literals in literal pools are possibly filled into the instruction cache, while instructions near literal pools could also be fetched into the data cache because the smallest cache management granularity is the size of a cache line. This useless but cached data deteriorates the performance of caches in a RISC processor. In this letter, we propose a find literal pool (FLP) algorithm to locate and record all literal pools in the text segment. Based on this information, we analyze the distribution of literal pools in SPEC CPU 2006 benchmarks and trace the process of caching literals to quantify the impacts of literal pools on caches. To optimize the cache performance influenced by literal pools, a relocate literal pool (RLP) algorithm is proposed to merge originally scattered literal pools into bigger ones without any hardware overhead. We evaluate the effectiveness of RLP with six SPEC 2006 benchmarks. Experimental results show that RLP reduces cache misses up to 24.4% in I-Cache and 38.72% in D-Cache compared to those of original literal pool layouts.