A tensor processing unit design for FPGA benchmarking
Sangram Kate · 2021
The recent exposure of use of FPGAs for deep learning applications have opened a wide range of use cases for FPGAs. The scalability and programmability of FPGAs are essential to update the hardware to encompass the state-of-the-art network architectures with special purpose units to accelerate the computation. However, these accelerator designs vary according to different design structures and properties. It is essential to understand the efficient FPGA architecture for a specific type of workload. This thesis provides an academic version of Google’s tensor processing unit (TPU v2) design as a benchmark for FPGA architecture evaluation. The thesis provides a reference microarchitecture for TPU v2 core design. The thesis uses Verilog-to-Routing (VTR) tool, which is a widely used open-source academic FPGA architecture analysis and research tool to perform the analysis of benchmarks on different types of FPGA architecture.