Fault diagnosis of Gate Level 2 – to – 1 Multiplexer in FinFET Technology
Chandrasekaran Saravanakumar, Usha Bhanu N · 2021 International Conference on System, Computation, Automation and Networking (ICSCAN) · 2021
This work deeply studies the identification of stuck at faults and its corresponding test vectors for a circuit. The circuit under consideration is a 2 – to – 1 multiplexer designed by NAND gate developed with the FinFET technology. The main constraint on design of the circuit is its area and power consumption. The design is simulated and its functionality is verified using Microwind 3.8. The simulation of PODEM algorithm for the designed circuit is proposed in this paper. The netlist generated from this simulation is adapted to simulate the PODEM algorithm to detect the faults. The simulation is carried out in MATLAB2019b and identified the fault location with a input test vector.