Low Latency NoC Switch using Modified Distributed Round Robin Arbiter
Ashok Kumar K, Sathian Dananjayan, Karunakar Reddy Vanga · Journal of Engineering Science and Technology Review · 2021
Switch design in NoC is a critical issue in intercommunication network of SoC because it is responsible for performance such as power consumption, area and latency.The performance of NoC switch is enhanced by reducing the number of input and out ports.By modifying and upgrading Minimal Adaptive Circuit Switching (MACS) NoC, the switch design is proposed thereby improving the performance and also flexibility.To achieve low latency and area overhead for NoC, a modified distributed round robin arbiter based switch is introduced, designed with Store and Forward packet switching and minimal adaptive routing.The proposed NoC switch with modified distributed round robin arbiter is implemented using Xilinx ISE 14.7 in vertex-6 (V6) FPGA and the results are compared with MACS.The proposed design shows a 58% higher operating frequencies and a 25% lesser area overhead when compared with MACS.