Design of Self-Refresh bitstream based on FPGA dynamic local reconfiguration
Zhimei Zhou, Yübo Wang, Chao Ma, Yue Zhang, Hao Xu, Yong Wan, Kui Xiong, Chen Feng · 2021 4th International Conference on Advanced Electronic Materials, Computers and Software Engineering (AEMCSE) · 2021
This article first introduces the implementation of FPGA dynamic partial reconfiguration, combined with the space radiation environment’s demand for FPGA configuration refresh, and analyzes the advantages and disadvantages of different refresh control systems. According to the understanding of the FPGA bitstream structure, this paper proposes a Self-Refresh bitstream design scheme based on FPGA dynamic partial reconfiguration and designs the corresponding bitstream. The simulation results show that the bitstream design scheme is easy to implement in FPGA and significantly reduces the refresh time.