FPGA Implementation of Power Efficient Floating Point Fused Multiply-Add Unit
K. Mounika, Padarthi Venkatramana · 2021
This paper deals with on-chip power reduction and area efficient fused floating point multiply-add unit, which is aimed to be used for 2D/3D graphics and scientific etc. applications. Floating point plays a vital role in Digital Signal Processor. On implementing fused floating point multiply-add, the total on-chip power between synthesis and implementation is reduced. By using fused floating point speed of the execution will be very fast. These designs are simulated and synthesized with VIVADO IP 2020.2. It achieves best on-chip power and less area. Synthesised results are encouraging.