Impact of gate input pulse width on FeFET-based reservoir computing
Z. Wang, Kasidit Toprasertpong, Zhijian Lin, Eishin Nako, Ryosho Nakane, Mitsuru Takenaka, Shinichi Takagi · IEEE Silicon Nanoelectronics Workshop · 2021
We experimentally demonstrate the relation between gate pulse width and computing performance in a physical reservoir computing system using a FeFET, where triangle pulses are input to the gate terminal and the time-series drain currents are treated as virtual nodes. The input signals with shorter pulse width lead to better memory capacity than those with longer one, which originates from extra information provided by charging/discharging current observed under fast-changing pulses.