Efficient VIA position optimization for yield enhancement
Hsi Min Liu, Yen Po Tseng, Chia Chien Lee, Chun-Sheng Tsai, Xiang Fang, Shou-Yuan Ma, Hung-Yueh Liao, Ling-Chieh Lin, Alex Pearson, Manish Khanna · 2021
We introduce a new algorithm (DFM Via Shift) to reposition vertical interconnect access (VIA) design patterns, considering the retargeted metal (both upper and lower layer) pattern, the user-defined max-shifting range, and the VIA design rule, for the purpose of achieving maximum metal coverage of VIAs. The DFM Via Shift algorithm considers VIAs that interact with each other based on spacing rules as a VIA cluster. All VIAs in a cluster are co-optimized, allowing for fully-covered VIAs with good positioning to be shifted to allow other, more critical VIAs to be optimized in some scenarios. We present the results of our research showing that the overall metal coverage of VIAs in 25nm node test chips can be significantly improved with repositioning. Nearly 95% of VIAs exposed out of metal after retargeting can be optimized to new, fully-covered positions in one of the test cases of the advanced node.