Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support
Qilin Si, Imtiaz Rashid, Benjamin Carrión Schäfer · 2021
State-of-the-art Coarse-Grain Runtime Reconfigurable Arrays (CGRRAs) can now be reconfigured every clock cycle. At the same time, CGRRA and traditional FPGA vendors have embraced High-Level Synthesis (HLS) to increase the design productivity and help designers with limited hardware development skills to program these devices. One of the advantages of HLS over traditional RT-level hardware design is that the HLS process automatically re-tunes the generated hardware circuit based on the target synthesis frequency. Moreover, a large pool of design candidates with different area vs. performance tradeoffs can be easily generated by setting different synthesis options in the form of synthesis directives (pragmas). These typically allow the designer to control how to synthesize arrays (registers or RAM), loops (unroll, not unroll or partially unroll) and functions (inline or not). This work leverages this and proposes a method to dynamically adapt the micro-architecture at runtime when the operating frequency changes to reduce the power consumption, while maximizing the throughput. Most, previous works on Dynamic Frequency Scaling (DFS) for FPGAs assume that the architecture is fixed. Results show that our proposed approach leads to faster circuits which consume a fraction of the power than just statically scaling the frequency of the static microarchitecture.