Full Custom Layout of Neural Network Processing Element Using Push Pull D Flip Flop and Modified Carry Look Ahead Adder
Adiwena Putra, Trio Adiono · 2021
This paper presents a full custom design of a 4-bit ANN processing element, implemented using 120 nm technology. The processing element consists of register, adder, and multiplier. The register is implemented using push-pull D flip-flop architecture, the adder is implemented using modified carry lookahead architecture, while the multiplier is implemented using the parallel architecture of the radix-4 booth. The processing element is fully functional and has been simulated with a 1 GHz clock frequency. The total area of the processing element is 3752.6 μm2with the worst path delay of 305 ps.