Energy Efficient NoC design through Supervised Machine Learning
D. Sorna Shanthi, Ashwani Kumar · Journal of Physics Conference Series · 2021
Abstract 3D Network On Chip(NoC) will provide high multi-core data processing with the minimal amount of energy consumption. It is necessary to consider the architectural limits of three-dimensional NoCs. A deep reinforced framework is proposed that uses router-less NoC for evaluation in the case study. The framework uses prior approaches that may be unreliable because of the difficulties with the design and search process, and the inflexibility that results because of space restrictions. The framework has better loop placements for networking chips with various design constraints. A Monte Carlo search tree is used to develop a Deep Neural Network that searches in parallel for a NoC design.