Mini Pool: Pooling hardware architecture using minimized local memory for CNN accelerators
Eunchong Lee, Sang-Seol Lee, Minyong Sung, Sung‐Joon Jang, Byoung-Ho Choi · 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) · 2021
Research to solve the problem of memory bandwidth shortage of convolutional neural network accelerators is continuously being studied with the development of deep neural network technology. We drastically eliminate the memory bandwidth of the pooling process through parallelization and propose a hardware structure that minimizes the amount of internal memory used for pooling. The proposed pooling hardware has identified that some constraints exist to minimize internal memory, but is applicable to most existing networks, and uses less than 60% of memory resources than conventional pooling hardware.