Physical Implementation of Square-Root-Carry-Select-Adder
Suneel Sankanatti, S Praveen · 2021
This paper mainly described about physical implementation of 8-bit Square-root-carry-select-adder (SRCSA) circuit. The SRCSA is designed using the Verilog HDL and implemented from RTL to GDSII. The functional verification of the SRCSA circuit is carried using Verilog (RTL file) and test bench in NCLaunch tool from cadence. The synthesis of SRCSA circuit is carried in Genus tool from Cadence, it's convert the RTL file to gate-level netlist. In back end design, physical implementation is carried out on Innovus tool from cadence. Later GDSII file can be generated. The reports are generated on power, area and timing during synthesis flow and physical implementation flow. After optimization during the physical implementation reported the power is 146.6mW, timing is 11593ps and area is 3389.6016um2. All process has been carried out using the 180nm technology.