Analysis and characterisation of design for testability methodologies for bipolar current mode logics
Padmapriya Kumar · PolyPublie (École Polytechnique de Montréal) · 2002
Emitter coupled logic -- Bipolar CML gates -- VersArray technology -- The importance of testing -- Design for testability -- Significance of developing DFT methods for bipolar CML -- Faults and defects -- Fault modelling & defect modelling for bipolar CML -- Types of test -- Studied DFT techniques -- Bias alteration stress technique -- Test bench setup for characterising BAS technique -- Simulation results -- Observations -- Methods attempted to increase the usable range of bias voltages -- Simulations taking process variations into account -- Summary and conclusions on BAS testing -- Imbalance testing technique & stress accumulation -- Functionality of and gates -- Imbalance test technique -- Imbalance types and limits -- Analysis of stuck at behaviour observed in defect-free and gates -- Characterisation of ITT on one gate -- Overcoming stress accumulation -- Sensitivity analysis -- Overview of the proposed testing technique -- Deriving the sensitivity of V out to various parameters -- Environmental factors -- The testing of the test chip -- Device Array block -- Test control block -- Test pattern generation flow and the testing process -- Test pattern generation and the testing of the test chip.