Property Driven Design based Verification for Register Transfer Level Hardware
R. Aarthi, C Aishwarya, M U Akash, P Krupasankar, G Yadukrishnan, J. P. Anita · 2021
The amount of features that could be put on a chip grew as a result of many innovations and developments. As a result, much more functional complexity is created. This motivates the need for architectural advancements with increased productivity. The “Property-Driven Design (PDD)” approach for Register Transfer Level i.e.,RTL hardware is described in this paper, which begins with aconceptual interface model and introduces property checking early in the design process. The proposed PDD approach generates abstracts properties from system architecture and uses them during the design phase to save time and effort on property testing. The new approach has a major benefit in that it provides an explicitly sound device model in addition to the RTL definition. By simplifying some complex research and evaluation activities in today's modern design flows, this helps to emancipate system-level models from mere models to golden concept models. Path predicate abstraction (PPA) produces time and abstract system models that could be combined to form abstract modeling techniques.