FPGA design of low resource consumed arbiter PUF
Zhenglin Liu, Liu Bojun, Zhaojun Lu, Tong Qiaoling · 2016
Low uniqueness and large resource consumption are two major problems of arbiter physical unclonable function(PUF).Referring to the structure of field-programmable gate array(FPGA)slice,a improved scheme of the traditional arbiter PUF was presented.It utilized the symmetric structure of slices to improve arbiter PUF’s uniqueness and took full advantage of the combinatorial logic resource of slice to reduce resource consumption.The inter-chip and intra-chip hamming distance were measured to evaluate the performance of a 64 bit arbiter PUF.Experiment results show that the improved arbiter PUF is suitable to be implemented on FPGA.It can reduce 62.5% resource consumption and its uniqueness value is close to the ideal value.