Profiling Techniques in Questasim and Design of a Profiler Hardware Module
Ashish Mishra, B Suhas, Suresh Kumar · SSRN Electronic Journal · 2017
Estimation of execution time for any module in software or in hardware guides the designer of its efficiency. The paper presents the profiling techniques present in QuestaSim hardware simulator for Field-Programmable Gate Array (FPGA) and System on Chips (SOCs). Different statistical and memory profiling techniques present in QuestaSim have been explained. An 8-bit Reduced Instruction Set Computing (RISC) processor has been designed for identifying the usefulness of the simulator. Various profiling reports have been generated and analyzed for the designed processor. The processor has been further extended by writing a module which counts the number of cycles taken by a unit. This module returns the count the number of times a function has been called. This module also gives the information such as how many different functions have been called, total number of different instructions, how many times each and function has been called.