A Low Complexity Parallel QC-LDPC Encoder
Xiaoxia Yao, Lintao Li, Jihong Liu, Qian Li · 2021 IEEE MTT-S International Wireless Symposium (IWS) · 2021
In this paper, a low complexity parallel QC (quasi-cyclic)-LDPC (low-density parity-check) Codes encoding algorithm and encoder architecture is introduced. In traditional encoder architectures, the complexity of multiplication operation of information sequence and generator matrix is very high. The proposed encoding algorithm bit selection (BS) directly selects the valid information bits according to position set of non-zero elements in the first column of the sub-matrix, which avoids the operation of invalid information bits. The proposed parallel QC-LDPC encoder architectures is realized for FPGA implementation based on CCSDS (7154, 8176) LDPC codes.