AREA EFFICIENT DESIGN OF A REDUNDANT BINARY MULTIPLIERUSING MODIFIED PARTIAL PRODUCT GENERATOR ANDCOMPRESSORS
Anand Anbalagan, K.K. Arun, J Muralidharan, S. Prabhakar Karthikeyan · Journal of Critical Reviews · 2020
Multiplier is an important factor for high speed arithmetic operations. Multipliers are designed by collection of Address and key element is arithmetic unit. Redundant binary multipliers are designed for product generation and compression operations. In our proposed method, modified booth encoding techniques is used for designing compressor and reduced multiplication operation. In this approach, carry free addition method so multiplier provides high performance. The proposed modified partial product generator is conventional modifier and additionally redundant bit is added for improve the performance. The simulation results shows our method significantly improve the area and the compressor. Here minimum 32 bits redundant binary multiplier is applied and reduce number of operands. The performance and power delay is compared with existing method and results are shown.