A Time Efficient Redundant Binary Adder with Modified Encoding Bits
Satya Ranjan Sahu, Manoranjan Pradhan · 2021
The paper presents the design of redundant binary adder using modified encoding bits. Sign magnitude encoding bit is one of them. The proposed adder deals with positive binary number and inverted encoding of negative binary number (IEN) to get output results. The hardware description language is used for synthesis of the proposed architecture using Xilinx 14.4 software. This structure is realized on vertex-4 xc4vfx12-12sf363FPGA device. The proposed architecture is found to be more time efficient than previously adder architecture.