A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash
Lanlan Cui, Xiaojian Liu, Fei Wu, Zhonghai Lu, Changsheng M. Xie · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2021
For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve an attractive tradeoff between implementation complexity and decoding performance. In this article, a novel low-bit-width decoding scheme is introduced. In this scheme, the quasi-cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower uncorrectable bit error rate (UBER) with a negligible increase in computational complexity, especially with low-precision input log-likelihood ratio (LLR).