A Pipelined Fused Processing Unit For Dsp Applications
Vinay Reddy N, Hema Chitra S · Zenodo (CERN European Organization for Nuclear Research) · 2015
This paper designs a processing element for FFT pr ocessor capable of operating on 32-bit double precision floating point numbers. Pipelining is performed on the computational elements of the DSP processor to enhance the throug hput. The performance of the Processing unit is increased by using the concept of fused arc hitecture on the sub modules � the dot product unit and the add sub unit. Pipelining incre ases the speed of the CE of the processor while fused operations claim area optimization. The DSP applications involve FFT Processors that make use of the butterfly operation s consisting of multiplications,additions,and subtractions of complex valued data (data is sp lit into real part and the imaginary part). The radix-2 and radix-4 butterflies are designed us ing fused architecture. The fused FFT butterflies are to be 20 percent speedier and 30 pe rcent smaller in area compared with the conventional method. The processing unit covers alm ost all the computations necessary for the processor https://www.ijiert.org/paper-details?paper_id=140116