A Compiler Perspective on Architectural Evolutions
Nicholas Mitchell, Larry Carter, Jeanne Ferrante · 1997
Certain architectural features either constrain or inhibit compiler optimizations. We suggest three hardware changes aimed to improve the situation, from a compiler's perspective. These changes involve redesigns of translation lookaside buffers, communication in memory hierarchies, and page mapping hardware for caches. Keywords--- cache, compiler, optimization, PlayDoh, prefetch, tiling, TLB I. Introduction Programmers and compilers use models to predict the consequences of programming and optimization choices. To take advantage of the features of its target, a back end optimizer needs to know various details of the architecture such as register count, instruction interaction and latencies, availability of special-purpose instructions and the ability to mask load latency with operations on independent data. A retargetable back end parameterizes optimizations based on this architectural model. Just as an architectural model lets the back end optimizer predict the performance of cert...