Enhanced Partially-Parallel LDPC Decoder for Near Earth Applications
Jing Kang, Bingbing Wang, Yufeng Zhang, Junshe An · 2021
This paper presents an enhanced partially-parallel low-density parity-check (LDPC) decoder based on Consultative Committee for Space Data Systems (CCSDS) standard for high speed near Earth applications. Architectural level optimization is exploited to reduce hardware complexity and increase decoding throughput. To enchance the parallelism of the partially-parallel decoder, high circulant weight submatrix of the parity check matrix (PCM) are partitioned into several identity matrices with corresponding cyclic-shifted value and processed separately. Furthermore, messages corresponding to adjacent rows of the cyclic-shifted identity matrix are stored in one memory entry, and low-complexity data aligners are designed between memories and processing units to avoid memory access conflicts. Hardware implementation of a (8176,7154) LDPC code on Xilinx Virtex-5 XC5VLX330 FPGA shows that the proposed decoder can achieve a decoding throughput of 1.02 Gb/s at 10 iterations.