A Length-Scalable Modular Multiplier Implemented with Multi-bit Scanning
Wen Jin, Ning Wu, Fen Ge, Liangkai Zhao · 2021 IEEE 4th International Conference on Electronics Technology (ICET) · 2021
Modular division and modular multiplication are the core operations in the elliptic curve cryptography (ECC). In recent years, reducing the hardware area, simplifying the hardware structure, and improving computing efficiency have become research hotspots. This paper proposes a modular multiplier based addition with the technology of Mulit_Bit Scanning, which supports prime field and binary field, and the length of this multiplier is up to 576-bit. This paper first analyzes the advantages and disadvantages of the add-based modular multiplication (AMM) and the multiply-based multiplication (MMM), and optimizes the AMM algorithm based multi-bit scanning; then designs the hardware structure based on the proposed algorithm. Moreover, the modular arithmetic unit is described at the RTL level by Verilog HDL, and based on the 180nm CMOS technology library for logic synthesis of all arithmetic units, the highest clock can reach 371 MHz(1.6~2.7 times of the others ), and the area being 45758 gates (0.29~0.51 times of the related works).