Design of HIMAC Coprocessor for HINOC3.0
Huang Jinjian, Qiu Zhiliang, Pan Weitao, Li Jun, Gao Zhikai, Bing Han, Zihao Xiong, Meng Dong · 2021 IEEE 6th International Conference on Computer and Communication Systems (ICCCS) · 2021
A high-performance HIMAC (HINOC Media Access Control layer) acceleration coprocessor for High-Performance Network over Coax (HINOC3.0) is presented in this paper. The design aims to provide wire-speed processing of up to 10G Ethernet frames. The design also completes the following functions: 1) Supports 2 to 16 channel bonding of the physical layer HIPHY (HINOC Physical layer); 2) Supports up to 128 terminal devices; 3) Supports the filtering and classification of Ethernet frames, completing operations such as assigning priority, discarding, and redirecting; 4) Supports mutual conversion between EMAC frame and HIMAC frame, by completing the encapsulating and splitting work; 5) Supports data exchange between EMAC interface and HIMAC interface. With the implementation of FPGAs, this HIMAC design can support wire-speed processing of up to 10G Ethernet frames and provide media access control layer functions for HINOC3.0.