An Agile Instruction Set Extension Method Based on the RISC-V Processor
Bowen Hu, Yun Chen, Xiaoyang Zeng · 2021 IEEE 4th International Conference on Electronics Technology (ICET) · 2021
The slowdown in Moore's Law scaling has triggered a growing awareness of domain-specific processors. One of the very promising techniques is the instruction set extension. RISC-V, as an open and simple instruction set architecture, is ideally suited as a basis for building domain-specific instruction-set processors. In this paper, we construct a framework based on the RISC-V processor that can receive data flow graph-based descriptions and automatically perform instruction set extensions. The framework is based on open-source software dependencies and is able to better interact with application codes, thus bridging the barrier between the application and the underlying microarchitecture of the processor. To evaluate the framework, a quantitative analysis of the Fast Fourier Transform algorithm is performed and the instruction set extension is applied with the framework proposed in this paper. By applying the methods in this paper to accelerate this commonly used digital signal processing algorithm, the runtime was reduced by 62%.