HIGH SPEED AND AREA-EFFECTIVE VLSI ARCHITECTURE OF THREE- OPERAND ADDER USING TANNER EDA TOO
S. SIVAKUMAR, JUTURU LAKSHMI, R. Keerthana, K. BHARATH · International Journal of Advanced Trends in Engineering Science and Technology · 2021
In different cryptography and pseudorandom bit generator (PRBG) methods, a three-operand binary adder is the basic functional unit for performing modular arithmetic. The carry-save adder is the most commonly used method for performing three-operand addition. The CS3A, on the other hand, has a long propagation delay due to the ripple-carry stage.Furthermore, a parallel prefix two-operand adder, such as the Han-Carlson (HCA), can be utilized for threeoperand addition, reducing the critical path delay dramatically at the cost of additional hardware. As a result, a new highspeed and area-efficient adder architecture is proposed, which performs the three-operand binary addition using precompute bitwise addition followed by carry-prefix computation logic, consuming significantly less area, consuming low power, and significantly reducing the adder delay. The TANNER EDA tool is used to implement the proposed design. The HC3A adder features a smaller area, lower power dissipation, and a shorter delay. We strive for low ADP and PDP with the proposed adder.