Design and Implementation of AS6802 Clock Synchronization System in TTE thernet
Jinlong Dong, Zhiliang Qiu, Weitao Pan, Min Wu, Jialiang Cao · 2021 IEEE 6th International Conference on Computer and Communication Systems (ICCCS) · 2021
Based on the research of the standard AS6802 protocol standard [1] and the interpretation of the existing Ethernet time synchronization solution on the FPGA hardware design platform, we designed and implemented a set of Ethernet clock synchronization system that supports the AS6802 standard. The system has been tested in a network environment, and the synchronization accuracy is less than 60 nanoseconds. Use FPGA to record the transparent clock, replacing the MAC IP core time stamping method in the previous Ethernet time synchronization solution. Therefore, this system is more flexible for the reception and transmission of Ethernet frame data, and reduces the dynamic delay introduced by the MAC IP core, which makes the synchronization accuracy higher, and has the characteristics of low cost and easy transplantation.