Towards the Basic Linear Algebra Unit : Replicating multi-dimensional FPUs to accelerate linear algebra applications
Nicolas Brunie · 2020
The ever improving silicon process nodes have provided chip manufacturer with a large available area. Once very expensive, floating-point units now constitute a small portion of the overall area of modern general purpose processors. In arithmetic heavy workloads, the processor peak performance is still directly proportional to this effective area. Chip manufacturers are always looking at ways to improve peak performance of each of their compute core. For regular arithmetic application, the introduction of vector extensions in ISA brought performance increases which linearly scale with core's memory bandwidth. Though, the size of vector has reached technical and usability limits. We suggest a new type of architectural extensions for CPU: the Basic Linear Algebra Unit instructions and associated execution unit (BLAU). This new arithmetic architecture considers packing matrices in general purpose vector registers and implementing elementary matrix operations as part of the processor standard arithmetic pipeline. We study the dimensions of matrices compatible with integration into General Purpose Processor vector registers and arithmetic pipeline. We introduce feasible implementations of such units in current technologies for various arithmetic formats. We show that, for specific applications, the processor arithmetic efficiency can be greatly increased by such extensions with algorithmic technics to limit the impact on memory bandwidth usage.