Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation
Irith Pomeranz · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2021
Two-cycle gate-exhaustive faults provide a comprehensive model for delay defects that are localized to gates (cells or subcircuits). However, the number of two-cycle gate-exhaustive faults can be excessive. Cell-aware faults are obtained by performing layout analysis of cells to select faults that are important to detect. This article suggests a complementary view of faults that are important to detect. Under this view, a two-cycle gate-exhaustive fault is important to detect if it can affect the circuit during functional operation. Such faults can be identified by generating functional broadside tests. To obtain unconstrained two-cycle tests, which are more compact and detect more faults than functional broadside tests, the article uses a test generation procedure that extracts test cubes from functional broadside tests, merges the test cubes into tests, and derives both broadside and skewed-load tests from the resulting test data. The procedure is iterative to allow a gradual increase in the number of tests and the number of detected two-cycle gate-exhaustive faults. Experimental results for benchmark circuits demonstrate the tradeoff explored by the procedure.