A Novel design of Nano scale TIEO based single layer full adder and full subractor in QCA paradigm
K Kalpana, B. Paulchamy, S. Chinnapparaj, K. Mahendrakan, A. Abdul Hayum · 2021
CMOS design dimension strongly decreased by reducing of transistor volume. CMOS transistor shall not be very much compressed and then their current size because combination results in actual bounds are abrupt transmit impact, Impurity difference, raise rate of fabrication process and temperature during process are the added important factors that cause, today MOS technology comes to an end. As per record quantum dot cellular automata technology provides a bright future resource which provides a precise shortly of approaching technic. Enormous capacity technic (QCA) is to make it CMOS due its bettered characteristics like energy smart, huge density and prompt execution. Addition and subtraction is important part of primary operations in ALU. Full adder and subractor is a basic element to design multiplier and divider circuit. A new plan for full adder and full subractor by three inputs EXOR gate logic towards single layer through minimum count of QCA cells is submitted. The proposed structures is stimulated in QCA designer tool and their power analysis done in QCA designer E tool.