Enabling OpenMP Task Parallelism on Multi-FPGAs
Ramon Nepomuceno, Renan Sterle, Guilherme Valarini, Marcio Machado Pereira, Hervé Yviquel, Guido Costa Souza De Araujo · 2021
FPGA-based accelerators have received increasing attention recently. Nevertheless, the amount of resources available on even the most powerful FPGA is still not enough to speed up very large workloads. To achieve that, FPGAs need to be interconnected in a Multi-FPGA architecture. However, programming such architecture is a challenging endeavor. This paper extends the OpenMP task-based computation offloading model to enable several FPGAs to work as a single Multi-FPGA architecture. Experimental results, for a set of OpenMP stencil applications running on a Multi-FPGA platform, have shown close to linear speedups as the number of FPGAs and IP-cores per FPGA increases.