Reconfigurable Synthesizable Synchronization FIFOs
Ameer Abdelhadi, He Li · 2021
We present a reconfigurable high-throughput synthesizable synchronization FIFO for crossing between asynchronous and synchronous timing domains. This FIFO is composed of reconfigurable mix-and-match components. The FIFO is fully synthesizable using standard-cell libraries and a standard design flow. A post-layout design throughput exceeds 1.2 G-transfer/sec when implemented in a 65nm CMOS process.