Address Hashing in Intel Processors
John D. McCalpin · 2018
To implement a distributed shared last-level cache, addresses must be distributed across the set of cache "slices" in a way that maintains an acceptable degree of uniformity for many common access patterns. This presentation reviews the properties of the address hashes used in Intel Xeon Phi x200 and Intel Xeon Scalable Processors as determined by microbenchmark experimentation. Several cases of conflicts are discussed, along with possible workarounds.