Synthesis and Implementation of IIR Filter using VHDL Language
Noor Talal Gadawe, T.A. Fathi, Sahar Lazim Qaddoori, Rasha Waleed Hamad · IOP Conference Series Materials Science and Engineering · 2021
Abstract VHDL is a hardware description language of different hardware architectures at divers’ levels of abstraction. The language is used for design, modelling, and investigation of hardware. In this paper, it is presented hardware implementation architectures of IIR filter using synthesizable VHDL. The MATLAB Filter Design and Analysis Tool (FDA Tool) is usedto calculate filter coefficients. Then, the filter is simulated and implemented on the Xilinx xc3s500efg320-4. A fixed-point number representation is used in the implementation of the filter. The proposed design of the filter includes two architectures: parallel architecture and programmable multiplexing architecture, each type has its advantages and disadvantages. In the results, some figures depending on the size of design (filter length) are introduced in the synthesis report.