High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator
Hankun Lv, Yuchen Ren, Yunhui Qiu, Wenbo Yin, Lingli Wang · 2020
This paper presents a high throughput and low latency multi-version management KVS accelerator, implemented on the FPGA-CPU heterogeneous architecture, supporting PUT, GET, DELETE and GET_RANGE operations. A pipelined Hash Engine architecture is proposed to improve the accelerator throughput and avoid data consistency issue. B-Tree processing engine is set in parallel and is designed in pipeline to improve PUT and DELETE throughputs. GET throughput is improved by the pipelined architecture which can make good use of the DMA bandwidth. The proposed accelerator implemented on Xilinx Kintex UltraScale FPGA KCU105 evaluation kit achieves 2.08× frequency at the cost of 1.36× resources and it can achieve 2.08 million key-version-value PUT and DELETE operations per second (Mops), which is 3.6× and 4.3× as high as the throughput of the state-of-the-art accelerator respectively. For GET operation, the proposed accelerator can reach 5.77 Mops which is 4.8× as high as the state-of-the-art accelerator.