Towards Row Sensitive DRAM Refresh through Retention Awareness
Tanmay Goel, Divyansh S. Maura, Kaustav Goswami, Shirshendu Das, Dip Sankar Banerjee · 2021
Dynamic Random Access Memory (DRAM) is the de facto choice for ram memories in modern day computing systems. It is based on capacitor technology, which is volatile in nature. Hence, these memories require periodic refreshing, usually al 64 ms, in order to ensure data persistence. Refreshing results in blocking of the memory device for performing normal read nr write operations. However, it has been found that not all cells of the device requires uniform refreshing at 64 ms. flue to shrinking of technologies, deviations are observed in nominal parameters which causes variations in retention and restoration time. In this paper, we propose a refeniion aware DRAM refreshing model, which is operated in auto-refresh (AR) mode of a DRAM device. We call the proposed model Lightweight Retention Time Aware Refreshing, or simply LRAR, which can be operated either in a deterministic or an approximate made while consuming a constant amount of hardware space. The lormer ensures consumption of least possible area in comparison to previously proposed works. While the latter is aimed tπ incorporate periodic refreshing for a newly emerged DRAM phenomenon called Variable Relention Time, or, VRT, which uses the basics of app i-ox ira tion. After extensive evaluation, we find that our proposed model reduces execution time of programs up tπ 11 %n (9.4% on average). The memory system's energy consumption is also reduced by an average of 11.5%, and refresh energy by an average of 73.6%n. We achieve the aforementioned gains al a modest area overhead of 7,24üjιm2(8.0118% of a 400mm2die) and storage overhead.