Hardware Software Co-Simulation of an AES-128 based Data Encryption in Image Processing Systems for the Internet of Things Environment
Kusum Lata, Sandeep Saini · 2020
Security of the data is a major challenge in the deployment and management of the Internet of Things (IoT) systems in the heterogeneous environment, where data gets transferred very widely and rapidly in multiple modes across the globe. Concomitant with the advancement of the technology, the number of devices and systems which are involved in transferring the image data has increased in the heterogeneous IoT environment. At present, image processing devices have become an integral part of the IoT edge devices which can collect the images and automatically share with the network. Because of the multifaceted usage of images in multimedia applications in the IoT environment, it is essential to protect the data from unauthorized access. The Advanced Encryption Standard (AES) is a well-established cryptography algorithm used in numerous applications to protect digital data. In this paper, we present a Hardware-Software Co-Simulation with Xilinx System Generator of an AES-128 bit encryption and decryption for IoT Edge devices. Hardware Co-Simulation makes it possible to integrate a design running in an FPGA directly into Simulink simulation. AES-128 bit algorithm has been implemented on the SPARTAN-6 (XC6SLX45-CSG324) FPGA board with XILINXISE software. Authors can get the successful results for image encryption and decryption both while implementing on grey and colored images. For Hardware Co-Simulation of AES-128 bit algorithm with Xilinx system generator, a point-to-point Ethernet approach is used. This implementation is done using Xilinx ISE14.2 and MATLAB 2011a for both grey image and colored image of size 448*298.