Combining Thread Throttling and Mapping to Optimize the EDP of Parallel Applications
Gustavo Paim Berned, Thiarles S. Medeiros, Matheus S. Serpa, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Philippe O. A. Navaux, Antonio Carlos Schneider Beck, Arthur F. Lorenzon · 2021
Thread-throttling and mapping strategies have been used together to make better use of hardware resources and improve the energy-delay product (EDP) of high-performance computing (HPC) systems. However, the design space exploration significantly grows with the increasing number of cores in those systems, making the task of finding the ideal number of active threads and allocating strategy a challenging task. On top of that, parallel applications present various patterns, such as irregularity, unbalanced computations, or high rates of communications. Given these considerations, we propose ETTM, an EDPaware thread-throttling and mapping optimization strategy that automatically finds an ideal combination of number of threads and thread mapping strategy. With the execution of eighteen well-known benchmarks on three multicore architectures, we show that EDP can be significantly improved when running applications with the solution found by EETM1.