Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC
Biruk B. Seyoum, Marco Pagani, Alessandro Biondi, Giorgio Buttazzo · 2021
Despite its benefits, hardware acceleration under dynamic partial reconfiguration (DPR) has not been fully leveraged by many system designers, mostly due to the complexities of the DPR design flow and the lack of efficient design tools to automate the design process. Furthermore, making such a design approach suitable for real-time embedded systems requires the need for extending the standard DPR design flow with additional design steps, which have to accurately account for the timing behavior of the software and hardware components of the design, as well as of the components of the computing platform (e.g., the reconfiguration interface).