High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory
Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima · 2021
Integrity checking is indispensable in the current technological age. One of the most popular algorithms for integrity checking is SHA-256. To achieve high performance, many applications generally design SHA-256 in hardware. However, the processing rate of SHA-256 is often low due to a large number of computations. Besides, data must be repeated in many loops to generate a hash, which requires transferring data multiple times between accelerator and off-chip memory if not using local memory. In this paper, an ALU combining fully parallel computation and pipeline layers is proposed to increase the SHA-256 processing rate. Moreover, the local memory is attached near ALU for reducing off-chip memory access during the iterations of computing. In the high hash rate, we design a SoC-based multicore SHA-256 accelerator. As a result, our proposed accelerator enhances throughput by more than 40% and be 2x higher hardware efficiency compared with the state-of-the-art design.